In a computing device, graphics data are typically provided by a central processing unit (CPU). The CPU may be part of a general computing architecture. The CPU may be involved in “processor-to-processor” multi-tasking techniques to process/render graphics. In particular, the CPU communicates and hands graphics data to a graphics processing unit (GPU), and the GPU renders (processes) the graphics data. The hand off between CPU and GPU may make use of semaphores, where semaphores are a variable or abstract type used for controlling access for multiple processes (i.e., multi-tasking).
The CPU may offload or send the graphics data for processing to memory, like dynamic random access memory (DRAM) for example. The hand off between CPU and GPU using semaphores, may rely on the graphics data being produced and consumed from the same memory (i.e., DRAM). The GPU accesses memory (i.e. DRAM) to receive the graphics data. This type of offload graphics command scheduling may involve sending command lists into a non-coherent memory (fabric) through memory mapped (MMIO) access. The non-coherent memory may then use a graphics translation table to translate the MMIO address to a DRAM address. The resulting translated access will be redirected to DRAM using the translated address. The non-coherent memory (fabric) may be considered as a “first space.” Coherent memory (fabric) is then used to notify the GPU, or a command scheduling graphics microcontroller of the GPU, that there is new work/graphics data to schedule. The coherent memory (fabric) may be considered as a “second space.” Because the new work notification occurs through coherent memory (fabric), and not non-coherent memory (fabric), a method is needed to ensure that the command list has been pushed from non-coherent memory MMIO memory back to DRAM before scheduling the work.
The command list is produced or sent to one space (i.e., non-coherent memory or fabric), but graphics data is consumed by the GPU in another space (coherent memory). Because two different spaces are involved for the command list, when the control is passed from CPU to GPU, the command list is not guaranteed to be visible via the coherent memory (i.e., coherent DRAM).